In the current state of technology, digital circuits are designed to address the increasing concern of controlling leakage current; especially when low current usage in the digital logic circuit is desired. High leakage current may result in reduced device operating time in the case of battery-powered devices. Therefore, there is a need for low leakage logic circuits.
A conventional 1.8V logic circuit, in the form of an inverter may be used as the low leakage logic circuit. The 1.8V low leakage logic circuit can be designed by connecting two Gallium Arsenide Hetero-junction Bipolar Transistors (GaAs HBTs) in a double inverter type logic circuit (hereafter referred to as Double Inverter Circuit). The double inverter circuits that are compatible with CMOS circuitry may be used to provide control voltages for high power Radio Frequency (RF) front-end transmitters.
FIG. 1 illustrates a prior art double inverter circuit 100. Double inverter circuit 100 includes a first transistor 105 and a second transistor 115. A first transistor 105 and a first resistor 110 connected as shown form a first circuit path. Similarly, a second transistor 115 and a second resistor 120 connected as shown form a second circuit path. When control voltage Vctrl is high, second transistor 115 turns ON which causes all current from the supply voltage to flow through second transistor 115 to ground. Thus, first transistor 105 turns (or remains) OFF. Therefore, the output of double inverter circuit 100 at output terminal 130 is high (Vcc—voltage drop across first resistor 110), resulting in an ON state of double inverter circuit 100. Output terminal 130 supplies logic voltage and bias current to any circuit (not shown) connected.
Similarly, when the control voltage Vctrl is low, first transistor 105 turns on and double inverter circuit 100 operates in the OFF-state providing no voltage at output terminal 130. Since, first transistor 105 is ON, it will conduct a small amount of current (corresponds to the leakage current) which is not desirable in the OFF-state operation of double inverter circuit 100.
In this prior art implementation, this leakage current is controlled by first resistor 110 and second resistor 120, which are connected to the collector terminals of first transistor 105 and second transistor 115 respectively. In order to maintain very low leakage current (<3 μA) in double inverter circuit 100, the values of first resistor 110 and second resistor 120 need to be in the mega Ohm (>1 MΩ) range or higher. This requirement places a limit on the current available from output terminal 130 of the double inverter circuit 100. In applications, such as high power switch bias in RF front-end transmitters, where high bias current might be required, the systems will fail to operate properly due to limited current sourcing capability from the double inverter circuit 100. In addition, the leakage current will increase proportionally with the number of logic circuits used in the systems.
In view of the foregoing, an advanced low leakage logic circuit is desirable that addresses the limitations of the standard CMOS compatible low leakage logic circuits.